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rt9002a/b/c 1 ds9002abc-04 april 2011 www.richtek.com features z z z z z low quiescent current (typically 70 a) z z z z z wide operating voltage ranges : 2.5v to 5.5v z z z z z ultra-fast transient response z z z z z tight load and line regulation z z z z z current limiting protection z z z z z thermal shutdown protection z z z z z only low esr ceramic capacitors required for stability z z z z z custom ldo v out1 , v out2 voltage available from 1.5v to 3.3v z z z z z custom v in detector available from 3.5v to 4v z z z z z rohs compliant and 100% lead (pb)-free pin configurations applications z cd/dvd-rom, cd/rw z wireless lan card/keyboard/mouse z battery-powered equipment z xdsl router dual low dropout regulator with detector ordering information general description the rt9002a/b/c is a dual-channel, low noise, and low dropout regulator. the first regulator is capable of sourcing 240ma, while the second regulator can source up to 500ma and includes a voltage detection function. the rt9002a/b/c performance is optimized for cd/dvd-rom, cd/rw or wireless communication supply applications. the rt9002a/b/c regulator is stable with output capacitors as low as 1 f. the other features include high output accuracy, ultra-fast transient response, tight load and line regulation, current limiting/thermal protection and high ripple rejection ratio. the rt9002a/b/c is available in sop-8 package requiring minimum board space and smallest components. typical application circuit (top view) sop-8 vin1 vout1 cd vin2 vout2 vdout gnd en1 2 3 4 5 8 7 6 note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. vin1 gnd vout1 rt9002a/b/c c out1 1uf 1uf vdout en1 c in1 cd v in1 v out1 1uf c in2 v in2 c out2 1uf v out2 vin2 vout2 cd chip enable 1 8 45 6 3 2 7 v in2 v dout 100k r1 rt9002a/b/c package type s : sop-8 lead plating system p : pb free g : green (halogen free and pb free) - output voltage : vout1/vout2 a : 2.5v/3.3v b : 1.5v/2.8v c : 2.5v/3.3v
rt9002a/b/c 2 ds9002abc-04 april 2011 www.richtek.com function block diagram functional pin description pin no. pin name pin function 1 vin1 channel 1 supply input. 2 vout1 channel 1 output voltage. 3 cd delay capacitor. 4 vin2 channel 2 supply voltage. 5 vout2 channel 2 output input. 6 vdout detector output voltage. (rt9002a = active high, rt9002b and rt9002c = active low) 7 gnd common ground. 8 en1 chip enable (active high) for channel 1. en1 current-limit and thermal protection mos driver + - vout1 shutdown and logic control vin1 error amplifier v ref current-limit and thermal protection mos driver + - vout2 vin2 error amplifier v ref gnd vd comparator + - cd vdout
rt9002a/b/c 3 ds9002abc-04 april 2011 www.richtek.com absolute maximum ratings (note 1) z supply input v oltage ------------------------------------------------------------------------------------------------ 6v z package thermal resistance (note 2) sop-8, ja ------------------------------------------------------------------------------------------------------------ 110 c/w z power dissipation, p d @ t a = 25 c sop-8 ------------------------------------------------------------------------------------------------------------------ 0.909w z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------- 260 c z junction temperature ----------------------------------------------------------------------------------------------- 150 c z storage temperature range -- ------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------------------- 2kv mm (machine mode) ------------------------------------------------------------------------------------------------ 200v electrical characteristics recommended operating conditions (note 4) z supply input voltage ------------------------------------------------------------------------------------------------ 2.5v to 5.5 v z chip enable input voltage ----------------------------------------------------------------------------------------- 0v to 5.5v z junction temperature range -------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------- ? 40 c to 125 c (v in = v out + 1v, whichever is greater, c in = 1 f, c out = 1 f, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit regulator 1 rt9002a 2.45 2.5 2.55 rt9002b 1.47 1.5 1.53 output voltage accuracy rt9002c v out1 i out1 = 30ma 2.45 2.5 2.55 v maximum output current i out1_max 240 -- -- ma load regulation (note 5) v lo ad1 1ma < i out1 < 100ma -- 1 -- mv v drop1_1 i out1 = 30ma -- 50 -- dropout voltage (note 6) v drop1_2 i out1 = 100ma -- 150 -- mv quiescent current (note 7) i q1 v in1 = v en1 = 3.5v, i out1 = 0ma -- 30 -- a standby current i stb1 v in1 = 3.5v , v en1 = 0v -- 0.1 1 a line regulation v li ne 1 v in1 = 3.5v to 5.5v, v in1 = v en1 , i out1 = 30ma -- 0.01 0.2 %/v power supply rejection rate psrr1 f = 100hz, i out1 = 100ma -- ? 60 -- db current limit i lim1 v in1 = v en1 = 5v -- 450 -- ma logic-low v il -- -- 0.6 en threshold voltage logic-high v ih 1.8 -- -- v thermal shutdown protection t sd1 -- 170 -- c to be continued
rt9002a/b/c 4 ds9002abc-04 april 2011 www.richtek.com parameter symbol test conditions min typ max unit thermal shutdown hysteresis t sd1 -- 40 -- c enable pin current i en v in = 3.5v, enable -- 0.1 1 a regulator 2 rt9002a 3.234 3.3 3.366 rt9002b 2.744 2.8 2.856 output voltage accuracy rt9002c v out2 i out2 = 30ma 3.234 3.3 3.366 v maximum output current i out2_max 500 -- -- ma load regulation (note 5) v load2 1ma < i ou t2 < 100ma -- 15 50 mv v drop2_1 i out2 = 30ma -- 50 90 dropout voltage (note 6) v drop2_2 i out2 = 100ma -- 150 200 mv quiescent current (note 7) i q2 v in2 = 4. 3v , i out2 = 0ma -- 40 -- a line regulation v lin e2 v in2 = 4.3v to 5.5v, i out2 = 30ma -- 0.01 0.2 % /v power supply rejection rate psrr2 f = 100hz, i out2 = 100ma -- ? 60 -- db current limit i lim2 v in2 = 5v -- 800 -- ma thermal shutdown protection t sd2 -- 170 -- c thermal shutdown hysteresis t sd2 -- 40 -- c detector rt9002a 3.528 3.6 3.672 rt9002b 3.822 3.9 3.978 detect fall voltage rt9002c v df 3.528 3.6 3.672 v hysteresis v hys v df x0.02 v df x0.05 v df x0.08 v rt9002a v dout = 0.5v, v in2 = 5.0v 7 12 -- rt9002b 4 8 -- sink current rt9002c i dout v dout = 0.5v, v in2 = 2.0v 4 8 -- ma
rt9002a/b/c 5 ds9002abc-04 april 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity test board of jedec 51-7 2s2p 4-layer thermal measurement standard. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. regulation is measured at constant junction temperature by using a 20ms current pulse. devices are tested for load regulation in the load range from 1ma to 100ma. note 6. the dropout voltage is defined as v in -v out , which is measured when v out is v out(normal) ? 100mv. note 7. quiescent, or ground current, is the difference between input and output currents. it is defined by i q = i in - i out under no load condition (i out = 0ma). the total current drawn from the supply is the sum of the load current plus the ground pin current.
rt9002a/b/c 6 ds9002abc-04 april 2011 www.richtek.com typical operating characteristics quiescent current vs. input voltage 25 27.5 30 32.5 35 37.5 40 42.5 45 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) quiescent current (ua) v out2 v out1 rt9002b output voltage vs. temperature 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 -50 -25 0 25 50 75 100 125 temperature output voltage (v) v out2 v out1 rt9002b ( c) quiescent current vs. input voltage 25 27.5 30 32.5 35 37.5 40 42.5 45 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) quiescent current (ua) v out2 v out1 rt9002a input voltage vs. detector voltage 0 1 2 3 4 5 6 7 0123456 input voltage (v) reset voltage (v) rt9002b input voltage vs. detector voltage 0 1 2 3 4 5 6 7 0123456 input voltage (v) reset voltage (v) rt9002a 125 output voltage vs. temperature 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 -50 -25 0 25 50 75 100 125 temperature output voltage (v) ( c) v out2 v out1 rt9002a
rt9002a/b/c 7 ds9002abc-04 april 2011 www.richtek.com nch driv er sink current vs. input voltage 0 10 20 30 40 50 60 0123456 input voltage (v) nch driver output current (ma) -40 c rt9002a 25 c 125 c nch driver sink current vs. input voltage 0 10 20 30 40 50 60 0123456 input voltage (v) nch driver output current (ma) rt9002b -40 c 25 c 125 c nch driver sink current vs. v ds 0 25 50 75 100 125 150 175 200 0123456 v ds (v) nch driver output current (ma) v dd = 5.5v rt9002a v dd = 5v v dd = 4.5v output delay time vs. load capacitance 0.01 0.1 1 10 100 1000 0.0000 0.0001 0.0010 0.0100 0.1000 load capacitance (uf) output delay time (ms) rt9002a output delay time vs. load capacitance 0.01 0.1 1 10 100 1000 0.0000 0.0001 0.0010 0.0100 0.1000 load capacitance (uf) output delay time (us) rt9002b nch driver sink current vs. v ds 0 10 20 30 40 50 60 70 80 90 100 110 0123456 v ds (v) nch driver output current (ma) v dd = 3.5v v dd = 3v v dd = 2.5v rt9002b v dd = 2v v dd = 1.5v v dd = 1v v dd = 0.5v
rt9002a/b/c 8 ds9002abc-04 april 2011 www.richtek.com load transient response time (500 s/div) i out1 (100ma/div) v out1 (5mv/div) v out2 (50mv/div) rt9002a i load = 10ma to 100ma line transient response time (250 s/div) v out (1v/div) 5 4 v out1 (20mv/div) v out2 (20mv/div) rt9002a boost i load = 50ma rt9002a, v out1 i load = 75ma en pin shutdown response time (100 s/div) shutdown voltage (5v/div) v out (1v/div) start up time (10 s/div) shutdown voltage (5v/div) v out (1v/div) rt9002a, v out1 i load = 75ma dropout voltage vs. load current 0 100 200 300 400 500 600 0 0.1 0.2 0.3 0.4 0.5 load current (a) dropout voltage (mv) rt9002c, v out2 = 3.3v -40 c 25 c 125 c dropout voltage vs. load current 0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 load current (ma) dropout voltage (mv) rt9002a, v out1 = 2.5v -40 c 25 c 125 c
rt9002a/b/c 9 ds9002abc-04 april 2011 www.richtek.com noise time (10ms/div) noise ( v/div) rt9002b, v out1 no load 600 400 200 0 -200 -400 -600 noise time (10ms/div) noise ( v/div) rt9002b, v out1 i out1 = 100ma 600 400 200 0 -200 -400 -600
rt9002a/b/c 10 ds9002abc-04 april 2011 www.richtek.com applications information like any low-dropout regulator, the external capacitors used with the rt9002 a/b/c must be carefully selected for regulator stability and performance. using a capacitor whose value is > 1 f on the rt9002 a/b/c input and the amount of capacitance can be increased without limit. the input capacitor must be located a distance of not more than 0.5 inch from the input pin of the ic and returned to a clean analog ground. any good quality ceramic can be used for this capacitor. the capacitor with larger value and lower esr (equivalent series resistance) provides better psrr and line-transient response. the output capacitor must meet both requirements for minimum amount of capacitance and esr in all ldos application. the rt9002 a/b/c is designed specifically to work with low esr ceramic output capacitor in space- saving and performance consideration. using a ceramic capacitor whose value is at least 1 f with esr is > 20m on the rt9002 a/b/c output ensures stability. the rt9002 a/b/c still works well with output capacitor of other types due to the wide stable esr range. figure 1. shows the curves of allowable esr range as a function of load current for various output capacitor values. output capacitor of larger capacitance can reduce noise and improve load transient response, stability, and psrr. the output capacitor should be located not more than 0.5 inch from the vout pin of the rt9002 a/b/c and returned to a clean analog ground. figure 1 enable the rt9002 a/b/c goes into sleep mode when the enable pin is in a logic low condition. during this condition, the pass transistor, error amplifier, and bandgap are turned off, reducing the supply current to 0.1 a typical. the enable pin may be directly tied to v in to keep the part on. the enable input is cmos logic and cannot be left floating. psrr the power supply rejection ratio (psrr) is defined as the gain from the input to output divided by the gain from the supply to the output. the psrr is found to be note that when heavy load measuring, supply will cause temperature. and temperature will cause output voltage. so the heavy load psrr measuring is include temperature effect. current limit the rt9002 a/b/c contains an independent current limiter, which monitors and controls the pass transistor's gate voltage, limiting the output1/2 current to 0.45/0.8a (typ.). the output can be shorted to ground indefinitely without damaging the part. thermal-shutdown protection thermal-shutdown protection limits total power dissipation in the rt9002 a/b/c . when the junction temperature exceeds t j = +170 c, the thermal sensor signals the shutdown logic, turning off the pass transistor and allowing the ic to cool. the thermal sensor turns the pass transistor on again after the ic's junction temperature cools by 40 c, resulting in a pulsed output during continuous thermal overload conditions. thermal-shutdown protection is designed to protect the rt9002 a/b/c in the event of fault conditions. for continual operation, do not exceed the absolute maximum junction temperature rating of t j = +125 c. ? ? ? ? ? ? = supply error gain log 20 psrr region of stable c out esr vs. load current 0.001 0.01 0.1 1 10 100 0 50 100 150 200 250 300 load current (ma) region of stable c out esr ( ? ) rt9002aps v in = 4.0v, v out2 = 3.3v c in = c out = 1uf/x7r unstable region stable region unstable region (simulation verify) region of stable c out esr ( )
rt9002a/b/c 11 ds9002abc-04 april 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a b j f h m c d i 8-lead sop plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.050 0.254 0.002 0.010 j 5.791 6.200 0.228 0.244 m 0.400 1.270 0.016 0.050

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